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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 54 Powerful Instructions - Most Single Clock Cycle Execution - 16 x 8 General Purpose Working Registers - Fully Static Operation - Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories - 512/1024 Bytes of In-System Programmable Flash Program Memory - 32 Bytes Internal SRAM - Flash Write/Erase Cycles: 10,000 - Data Retention: 20 Years at 85oC / 100 Years at 25oC Peripheral Features - One 16-bit Timer/Counter with Prescaler and Two PWM Channels - Programmable Watchdog Timer with Separate On-chip Oscillator - 4-channel, 8-bit Analog to Digital Converter (1) - On-chip Analog Comparator Special Microcontroller Features - In-System Programmable (2) - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Supply Voltage Level Monitor with Interrupt and Reset - Internal Calibrated Oscillator I/O and Packages - 6-pin SOT: Four Programmable I/O Lines Operating Voltage: - 1.8 - 5.5V Programming Voltage: - 5V Speed Grade - 0 - 4 MHz @ 1.8 - 5.5V - 0 - 8 MHz @ 2.7 - 5.5V - 0 - 12 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: * 200A at 1MHz and 1.8V - Idle Mode: * 25A at 1MHz and 1.8V - Power-down Mode: * < 0.1A at 1.8V
*
*
*
8-bit Microcontroller with 512/1024 Bytes In-System Programmable Flash ATtiny4/5/9/10 Preliminary
* * * *
* *
Note:
1. The Analog to Digital Converter (ADC) is available in ATtiny5/10, only 2. At 5V, only
8127CS-AVR-10/09
1. Pin Configurations
Figure 1-1. Pinout of ATtiny4/5/9/10
SOT-23
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 2 3 6 5 4 PB3 (RESET/PCINT3/ADC3) VCC PB2 (T0/CLKO/PCINT2/INT0/ADC2)
1.1
1.1.1
Pin Description
VCC Supply voltage.
1.1.2
GND Ground.
1.1.3
Port B (PB3..PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pullup resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 36.
1.1.4
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 16-4 on page 119. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.
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ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
2. Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram
VCC RESET
PROGRAMMING LOGIC
PROGRAM COUNTER
INTERNAL OSCILLATOR
CALIBRATED OSCILLATOR
PROGRAM FLASH
STACK POINTER
WATCHDOG TIMER
TIMING AND CONTROL
INSTRUCTION REGISTER
SRAM
RESET FLAG REGISTER
INSTRUCTION DECODER
GENERAL PURPOSE REGISTERS
X Y Z
MCU STATUS REGISTER
CONTROL LINES
TIMER/ COUNTER0
INTERRUPT UNIT ALU
ISP INTERFACE
STATUS REGISTER 8-BIT DATA BUS
DATA REGISTER PORT B
DIRECTION REG. PORT B
ANALOG COMPARATOR
ADC
DRIVERS PORT B
PB3:0
GND
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3
8127CS-AVR-10/09
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The onchip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits.
2.1
Comparison of ATtiny4, ATtiny5, ATtiny9 and ATTINY10
A comparison of the devices is shown in Table 2-1. Table 2-1. Differences between ATtiny4, ATtiny5, ATtiny9 and ATTINY10
Flash 512 bytes 512 bytes 1024 bytes 1024 bytes ADC No Yes No Yes Signature 0x1E 0x8F 0x0A 0x1E 0x8F 0x09 0x1E 0x90 0x08 0x1E 0x90 0x03
Device ATtiny4 ATtiny5 ATtiny9 ATTINY10
4
ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
3.4
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized.
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8127CS-AVR-10/09
4. Register Summary
Address
0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Name
SREG SPH SPL CCP RSTFLR SMCR OSCCAL Reserved CLKMSR CLKPSR PRR VLMCSR NVMCMD NVMCSR WDTCSR Reserved GTCCR TCCR0A TCCR0B TCCR0C TIMSK0 TIFR0 TCNT0H TCNT0L OCR0AH OCR0AL OCR0BH OCR0BL ICR0H ICR0L Reserved Reserved ACSR Reserved ADCSRA ADCSRB ADMUX Reserved ADCL Reserved DIDR0 Reserved EICRA EIFR EIMSK PCICR PCIFR PCMSK Reserved Reserved Reserved PORTCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PUEB PORTB DDRB PINB
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
Page 12 Page 12 Page 12 Page 12
Stack Pointer High Byte Stack Pointer Low Byte CPU Change Protection Byte - - - - - - VLMF - NVMBSY WDIF - TSM COM0A1 ICNC0 FOC0A - - - - - - - - VLMIE - - WDIE - - COM0A0 ICES0 FOC0B - - - WDP3 - - COM0B1 - - ICIE0 ICF0 - - - - COM0B0 WGM03 - - - - - - - - - - - - - - - - - WDRF SM2 - - CLKPS3 - - - WDE - - - WGM02 - - - NVM Comman - WDP2 - - - CS02 - OCIE0B OCF0B - WDP1 - - WGM01 CS01 - OCIE0A OCF0A - WDP0 - PSR WGM00 CS00 - TOIE0 TOV0 - SM1 - - CLKPS2 - VLM2 EXTRF SM0 - CLKMS1 CLKPS1 PRADC VLM1 PORF SE - CLKMS0 CLKPS0 PRTIM0 VLM0
Page 34 Page 25 Page 21 Page 21 Page 22 Page 26 Page 33 Page 115 Page 115 Page 32 Page 79 Page 73 Page 75 Page 76 Page 78 Page 79 Page 77 Page 77 Page 77 Page 77 Page 77 Page 77 Page 78 Page 78
Oscillator Calibration Byte
Timer/Counter0 - Counter Register High Byte Timer/Counter0 - Counter Register Low Byte Timer/Counter0 - Compare Register A High Byte Timer/Counter0 - Compare Register A Low Byte Timer/Counter0 - Compare Register B High Byte Timer/Counter0 - Compare Register B Low Byte Timer/Counter0 - Input Capture Register High Byte Timer/Counter0 - Input Capture Register Low Byte - - ACD - ADEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ADSC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACO - ADATE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACI - ADIF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACIE - ADIE - - - - ADC3D - - - - - - PCINT3 - - - - - - - - - - - - PUEB3 PORTB3 DDRB3 PINB3 - - ACIC - ADPS2 ADTS2 - - - ADC2D - - - - - - PCINT2 - - - - - - - - - - - - PUEB2 PORTB2 DDRB2 PINB2 - - ACIS1 - ADPS1 ADTS1 MUX1 - - ADC1D - ISC01 - - - - PCINT1 - - - BBMB - - - - - - - - PUEB1 PORTB1 DDRB1 PINB1 - - ACIS0 - ADPS0 ADTS0 MUX0 -
Page 81 Page 93 Page 94 Page 93 Page 95
ADC Conversion Result - ADC0D - ISC00 INTF0 INT0 PCIE0 PCIF0 PCINT0 - - - - - - - - - - - - PUEB0 PORTB0 DDRB0 PINB0
Page 82, Page 95 Page 37 Page 38 Page 38 Page 39 Page 39 Page 39
Page 50
Page 50 Page 51 Page 51 Page 51
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ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. The ADC is available in ATtiny5/10, only.
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8127CS-AVR-10/09
5. Instruction Set Summary
Mnemonics
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID LSL LSR ROL ROR ASR SWAP BSET Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b A, b A, b s, k s, k k k k k k k k k k k k k k k k k k k Rd Rd Rd Rd Rd Rd s k
Operands
Rd, Rr Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add without Carry Add with Carry Subtract without Carry Subtract Immediate Subtract with Carry
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S None None None None None None I None Z, C,N,V,S,H Z, C,N,V,S,H Z, C,N,V,S,H None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V,H Z,C,N,V Z,C,N,V,H Z,C,N,V Z,C,N,V None SREG(s)
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3/4 3/4 4/5 4/5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 1 1 1 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC(15:0) Z, PC(21:16) 0 PC PC + k + 1 PC(15:0) Z, PC(21:16) 0 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (I/O(A,b)=0) PC PC + 2 or 3 if (I/O(A,b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1
Subtract Immediate with Carry Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Exclusive OR One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
Mnemonics
BCLR SBI CBI BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV LDI LD LD LD LD LD LD LD LD LD LDS ST ST ST ST ST ST ST ST ST STS IN OUT PUSH POP Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd, Z Rd, Z+ Rd, -Z Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Z, Rr Z+, Rr -Z, Rr k, Rr Rd, A A, Rr Rr Rd Copy Register Load Immediate Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Store Direct from SRAM Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment. Store Indirect and Pre-Decrement Store Direct to SRAM In from I/O Location Out to I/O Location Push Register on Stack Pop Register from Stack Break No Operation Sleep Watchdog Reset (see specific descr. for Sleep) (see specific descr. for WDR) Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (k) Rr Rd I/O (A) I/O (A) Rr STACK Rr Rd STACK (see specific descr. for Break) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1/2 2 2/3 1/2 2 2/3 1/2 2 2/3 1 1 1 2 1 1 2 1 1 2 1 1 1 2 2 1 1 1 1 s A, b A, b Rr, b Rd, b
Operands
Flag Clear Set Bit in I/O Register Clear Bit in I/O Register
Description
SREG(s) 0 I/O(A, b) 1 I/O(A, b) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Operation
Flags
SREG(s) None None T None C C N N Z Z I I S S V V T T H H
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow. Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS BREAK NOP SLEEP WDR
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8127CS-AVR-10/09
6. Ordering Information
6.1 ATtiny4
Speed (MHz) 12 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny4-TSHR(3)(4) Package(1) 6ST1 Operational Range Industrial (-40C to 85C)(4)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Topside marking for ATtiny4: T4x (x stands for "die revision"). 4. Bottomside marking for ATtiny4: zHzzz [H stands for (-40C to 85C)].
Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
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ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
6.2 ATtiny5
Speed (MHz) 12 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny5-TSHR(3)(4) Package(1) 6ST1 Operational Range Industrial (-40C to 85C)(4)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Topside marking for ATtiny5: T5x (x stands for "die revision"). 4. Bottomside marking for ATtiny5: zHzzz [H stands for (-40C to 85C)].
Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
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8127CS-AVR-10/09
6.3
ATtiny9
Speed (MHz) 12 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny9-TSHR(3)(4) Package(1) 6ST1 Operational Range Industrial (-40C to 85C)(4)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Topside marking for ATtiny9: T9x (x stands for "die revision"). 4. Bottomside marking for ATtiny9: zHzzz [H stands for (-40C to 85C)].
Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
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ATtiny4/5/9/10
8127CS-AVR-10/09
ATtiny4/5/9/10
6.4 ATTINY10
Speed (MHz) 12 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATTINY10-TSHR(3)(4) Package(1) 6ST1 Operational Range Industrial (-40C to 85C)(4)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Topside marking for ATTINY10: T10x (x stands for "die revision"). 4. Bottomside marking for ATTINY10: zHzzz [H stands for (-40C to 85C)].
Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)
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8127CS-AVR-10/09
7. Packaging Information
7.1 6ST1
D 6 5 4 A
E
E1
Pin #1 ID
A2 A
A
0.10 C
SEATING PLANE
1 b
2 e
3
A1
C
Side View
Top View
A2
A
0.10 C
SEATING PLANE
0.25
SEATING PLANE
c
A1
C
View A-A
SEE VIEW B
O
C
L
View B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A A1 A2 D E E1
Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end. 3. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm 4. Die is facing down after trim/form.
NOM - - - 2.90 2.80 1.60 0.45 0.95 BSC - - -
MAX 1.45 0.15 1.30 3.00 3.00 1.75 0.55 0.50 0.20 8
NOTE
- 0 0.90 2.80 2.60 1.50 0.30 0.30 0.09 0
2
L e b c
3
6/30/08 TITLE 6ST1, 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) GPC TAQ DRAWING NO. 6ST1 REV. A
Package Drawing Contact: packagedrawings@atmel.com
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ATtiny4/5/9/10
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ATtiny4/5/9/10
8. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device.
8.1
8.1.1
ATtiny4
Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Lock bits re-programming 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level.
8.1.2
Rev. A - C Not sampled.
8.2
8.2.1
ATtiny5
Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Lock bits re-programming 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level.
8.2.2
Rev. A - C Not sampled.
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8127CS-AVR-10/09
8.3
8.3.1
ATtiny9
Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Lock bits re-programming 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level.
8.3.2
Rev. A - C Not sampled.
8.4
8.4.1
ATTINY10
Rev. C - D * ESD HBM (ESD STM 5.1) level 1000V * Lock bits re-programming 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level.
8.4.2
Rev. A - B Not sampled.
16
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ATtiny4/5/9/10
9. Datasheet Revision History
9.1 Rev. 8127C - 10/09
1. Updated values and notes: - Table 16-1 in Section 16.2 "DC Characteristics" on page 116 - Table 16-3 in Section 16.4 "Clock Characteristics" on page 118 - Table 16-6 in Section 16.5.2 "VCC Level Monitor" on page 119 - Table 16-9 in Section 16.8 "Serial Programming Characteristics" on page 121 2. Updated Figure 16-1 in Section 16.3 "Speed Grades" on page 117 3. Added Typical Characteristics Figure 17-36 in Section 17.2.7 "Analog Comparator Offset" on page 140. Also, updated some other plots in Typical Characteristics. 4. Added topside and bottomside marking notes in Section 6. "Ordering Information" on page 10, up to page 13 5. Added ESD errata, see Section 8. "Errata" on page 15 6. Added Lock bits re-programming errata, see Section 8. "Errata" on page 15
9.2
Rev. 8127B - 08/09
1. Updated document template 2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9 3. Added section: - "Comparison of ATtiny4, ATtiny5, ATtiny9 and ATTINY10" on page 4 4. Updated sections: - "ADC Clock - clkADC" on page 18 - "Starting from Idle / ADC Noise Reduction / Standby Mode" on page 20 - "ADC Noise Reduction Mode" on page 24 - "Analog to Digital Converter" on page 25 - "SMCR - Sleep Mode Control Register" on page 25 - "PRR - Power Reduction Register" on page 26 - "Alternate Functions of Port B" on page 48 - "Overview" on page 83 - "Physical Layer of Tiny Programming Interface" on page 96 - "Overview" on page 107 - "ADC Characteristics (ATtiny5/10, only)" on page 120 - "Supply Current of I/O Modules" on page 122 - "Register Summary" on page 6 - "Ordering Information" on page 10 5. Added figure: - "Using an External Programmer for In-System Programming via TPI" on page 97 6. Updated figure: - "Data Memory Map (Byte Addressing)" on page 15 7. Added table: - "Number of Words and Pages in the Flash (ATtiny4/5)" on page 109
17
8127CS-AVR-10/09
8. Updated tables: - "Active Clock Domains and Wake-up Sources in Different Sleep Modes" on page 23 - "Reset and Interrupt Vectors" on page 35 - "Number of Words and Pages in the Flash (ATtiny9/10)" on page 109 - "Signature codes" on page 110
9.3
Rev. 8127A - 04/09
1. Initial revision
18
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ATtiny4/5/9/10
19
8127CS-AVR-10/09
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8127CS-AVR-10/09

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